//+FHDR-------------------------------------------------------------------------
//            __     __ __                  ____     ___ ___
//           |  |   |  /__| ____ ___ ___   /    \   /  ____/
//           |  \___/  |  /   __    __   \/  __  \ /  /
//           |   ___   |  |  /  \  /  \     /__\  (  <
//           |  /   \  |  |  |  |  |  |    /    \     \____
//           |__|   |__ __ __|  |__|  |___/      \__ __ ___\ 2.0                     
//------------------------------------------------------------------------------
//-- Module Name     :    fp_bus_ctrl
//-- Hierarchy       :    frame_process - * - fp_bus_ctrl
//-- Description     :    适应分组处理模块乒乓部分的修改                                            
//                                                                              
//-- Last Modified   : 2013-01-29 19:55
//-- Revision history:                                                          
//     Date               Author       Description                              
//     2012-12-21 09:43   Tiger          Initialize code
//-FHDR-------------------------------------------------------------------------

/***************************************************************/
//     本模块完成向总线、捕获、广播fifo传送数据，同时执行流分类
//     分配的指令码操作
/***************************************************************/
//必须顺序处理帧的指令信息
//三种处理方式：丢弃、重定向到cpu、复制到cpu、交给调度模块
//所有处理的开始都以调度模块给出的trans_start为起始信号
//需要丢弃或者重定向到cpu的帧调度模块也会给出trans_start
//主要目的是：为了避免本模块处理不需要交给调度模块的帧时调度模块给出下一帧的处理要求
//此时无法做出响应，出现丢帧问题。
`timescale 1ns/100ps

module fp_bus_ctrl(
                    input wire clk,
                    input wire rst_n,

                    //与action_fifo模块的接口
                    input wire [75:0]action_fifout_q,
                    output reg action_fifout_rden,
                    
                    //与RAM模块接口,分组处理模块的RAM
                    input wire [262:0] rd_data_i,
                    input wire rd_rdy,
                    // output reg rd_en,
                    output reg rd_en,
                    output reg trans_ready,
                    //与调度模块的接口
                    input wire trans_start,
					input wire discard_start,
                    output wire[262:0] bus_data_o,
                    output reg bus_data_val_o,
                    output reg bus_data_end_o,
                    output wire [10:0] frame_len_bus,

                    //与捕获模块的接口
                    input wire capture_rdy,
                    output wire [262:0] capture_data_o,
                    output reg capture_dval,
                    output wire cpt_en,
                    output wire[10:0] cpt_frame_len,

                    //帧信息信号
                    input wire frame_length_valid,
                    input wire [10:0] frame_length,

                    //output state==IDLE
                    output reg frame_rd_end
                   );

parameter IDLE                          = 8'b00000001;                  
parameter DISCARD                       = 8'b00000010;
parameter CAPTURE_TRANS_UP_ADDR_INI     = 8'b00000100;
parameter CAPTURE_TRANS_UP              = 8'b00001000;
parameter BUS_TRANS_INI                 = 8'b00010000;
parameter BUS_TRANS                     = 8'b00100000;
parameter BUS_CAPTURE_TRANS_INI         = 8'b01000000;
parameter BUS_CAPTURE_TRANS             = 8'b10000000;

//**********************reg****************************
(*mark_debug = "true"*) reg  [7:0] bus_ctrl_cstate;
(*mark_debug = "true"*) reg  [7:0] bus_ctrl_nstate;

reg[10:0] frame_length_r,frame_length_r_d1,frame_length_r_d2;
reg[10:0] frame_length_cnt,frame_cnt_send;
reg action_en,action_en_d1,action_en_d2;
reg action_last,action_last_d1;
reg[ 31:0] value;
reg[ 31:0] mask;
reg[  5:0] word_offset,word_offset_d1; //字偏移，以16-bit为单位
reg[  2:0] operation,operation_d1,operation_d2;
reg[262:0] data_reg;
reg[ 31:0] data_reg_d1,data_reg_d2; 
reg[223:0] rd_data_d1;
reg[255:0] bus_data_r;
reg[255:0] capture_data_r;
reg[  4:0] mod;
reg sop,eop;
reg rd_en_d1,rd_en_d2;

reg cap_flag,cap_flag_d1,cap_flag_d2 ;
reg bus_flag,bus_flag_d1,bus_flag_d2 ;
reg frame_length_ren;
reg data_end;
reg [262:0] rd_data_i_sample;
reg rd_en_pos;

reg add_one_clk,add_one_clk_d1;
//*********************wire************************
wire[10:0] frame_length_rd;
wire[262:0] rd_data;
//状态机
always @ ( posedge clk or negedge rst_n )
  if(~rst_n)
    bus_ctrl_cstate <=  IDLE;
  else
    bus_ctrl_cstate <=  bus_ctrl_nstate;
//action_fifout_q
//删除[75]--复制[74]--重定向[73]--插、修、删[72:70]--字偏移[69:64]--掩码[63:32]--值[31:0]
always @ (*)
begin
  if(~rst_n)
    bus_ctrl_nstate = IDLE;
  else 
  case(bus_ctrl_cstate)
    IDLE:  //所有的帧搬移都已trans_start开始
      //if(add_one_clk_d1) 
      //  bus_ctrl_nstate = IDLE;
      if(action_fifout_q[73] && !action_fifout_q[74] && capture_rdy && trans_start)     //当数据帧非插入帧时重定向到cpu
    	bus_ctrl_nstate = CAPTURE_TRANS_UP; //动作指令为重定向到cpu
      else if(trans_start && action_fifout_q[74] && capture_rdy)  //当数据帧非插入帧时复制到cpu：actionexe修改
    	bus_ctrl_nstate = BUS_CAPTURE_TRANS; //读取action_fifo模块，产生的结果为直接丢弃或重定向到cpu
      else if((action_fifout_q[75] || discard_start) && trans_start)   //动作指令为丢弃
    	bus_ctrl_nstate = DISCARD;
      else if(trans_start)
        bus_ctrl_nstate = BUS_TRANS;
      else 
        bus_ctrl_nstate = IDLE; 
    DISCARD:
      if(rd_data[261])
        bus_ctrl_nstate = IDLE;
      else 
        bus_ctrl_nstate = DISCARD;
    
    CAPTURE_TRANS_UP:
      if(rd_data[261])
        bus_ctrl_nstate = IDLE;
      else 
        bus_ctrl_nstate = CAPTURE_TRANS_UP;

    BUS_TRANS:
      if(rd_data[261])
        bus_ctrl_nstate = IDLE;
      else 
        bus_ctrl_nstate = BUS_TRANS;

    BUS_CAPTURE_TRANS:
      if(rd_data[261])
        bus_ctrl_nstate = IDLE;
      else 
        bus_ctrl_nstate = BUS_CAPTURE_TRANS;
    default:
      bus_ctrl_nstate = IDLE;
  endcase
end
//得到当前帧的长度信息
always@(posedge clk or negedge rst_n)
begin
  if(~rst_n)
    frame_length_r <= 11'd0;
  else if(bus_ctrl_cstate == IDLE)
    case(action_fifout_q[72:70])
      3'b100:frame_length_r <= frame_length_rd+11'd4;
      3'b010:frame_length_r <= frame_length_rd;
      3'b001:frame_length_r <= frame_length_rd-11'd4;
      default:frame_length_r <= frame_length_rd;
    endcase
  else 
    frame_length_r <= frame_length_r;
end


always@(posedge clk or negedge rst_n)
begin
  if(~rst_n)
    add_one_clk <= 1'b0;
  else if(bus_ctrl_nstate == IDLE) begin
    add_one_clk <= 1'b0;
  end
  else if(bus_ctrl_cstate == IDLE) begin
    if(action_fifout_q[72:70] == 3'b100 && (((&frame_length_rd[4:2]) & (|frame_length_rd[1:0])) | (~(&frame_length_rd[4:0]))) && trans_start) begin
      add_one_clk <= 1'b1;
    end
    else begin
      add_one_clk <= 1'b0;
    end
  end
  else begin
    add_one_clk <= add_one_clk;
  end
end

always@(posedge clk or negedge rst_n)
  if(~rst_n)
    begin
      frame_length_r_d1 <= 11'd0;
      frame_length_r_d2 <= 11'd0;
      add_one_clk_d1    <= 1'b0;
    end
  else 
    begin
      add_one_clk_d1    <= add_one_clk;
      frame_length_r_d2 <= frame_length_r_d1;
      frame_length_r_d1 <= frame_length_r;
    end
//读帧长信息fifo的使能信号
always@(posedge clk or negedge rst_n)
begin
  if(~rst_n)
    frame_length_ren <= 1'b0;
  else if(bus_ctrl_cstate == IDLE && bus_ctrl_nstate != IDLE)
    frame_length_ren <= 1'b1;
  else 
    frame_length_ren <= 1'b0;
end
//是否为捕获阶段
always@(posedge clk or negedge rst_n) begin
  if(~rst_n)
    cap_flag <= 1'b0;
  else if(bus_ctrl_nstate == CAPTURE_TRANS_UP ||bus_ctrl_nstate == BUS_CAPTURE_TRANS)
    cap_flag <= 1'b1;
  else if(bus_ctrl_nstate == BUS_TRANS || bus_ctrl_nstate == DISCARD || (bus_ctrl_nstate == IDLE && (~add_one_clk)))
    cap_flag <= 1'b0;
  else 
    cap_flag <= cap_flag;
end

always@(posedge clk or negedge rst_n) begin
  if(~rst_n) begin
    cap_flag_d1 <= 1'b0;
    cap_flag_d2 <= 1'b0;
  end
  else begin 
    cap_flag_d1 <= cap_flag;
    cap_flag_d2 <= cap_flag_d1;
  end
end

//是否为总线搬移阶段
always@(posedge clk or negedge rst_n) begin
  if(~rst_n)
    bus_flag <= 1'b0;
  else if( bus_ctrl_nstate == BUS_TRANS || bus_ctrl_nstate == BUS_CAPTURE_TRANS)
    bus_flag <= 1'b1;
  else if(bus_ctrl_nstate == CAPTURE_TRANS_UP || bus_ctrl_nstate == DISCARD)
    bus_flag <= 1'b0;
  else 
    bus_flag <= bus_flag;
end

always@(posedge clk or negedge rst_n) begin
  if(~rst_n) begin
    bus_flag_d1 <= 1'b0;
    bus_flag_d2 <= 1'b0;
  end
  else begin
    bus_flag_d1 <= bus_flag;
    bus_flag_d2 <= bus_flag_d1;
  end
end

//action_fifo读使能信号
//在idle状态跳转后读action_fifo
always@(posedge clk or negedge rst_n) begin
  if(~rst_n)
    action_fifout_rden <= 1'b0;
  else if(bus_ctrl_cstate == IDLE && bus_ctrl_nstate != IDLE)
    action_fifout_rden <= 1'b1;
  else 
    action_fifout_rden <= 1'b0;
end

//读数据打一拍
always@(posedge clk or negedge rst_n)
begin
  if(~rst_n)
    rd_data_i_sample <= 263'b0;
  else 
    rd_data_i_sample <= rd_data_i;
end

//读数据使能,每次读一帧数据，不能多读
always@(posedge clk or negedge rst_n)
begin
  if(~rst_n)
    rd_en <= 1'b0;
  else if(bus_ctrl_cstate == IDLE && bus_ctrl_nstate != IDLE)
    rd_en <= 1'b1;
  else if(rd_data[261] == 1'b1)
    rd_en <= 1'b0;
  else 
    rd_en <= rd_en;
end
//读数据使能打一拍
always@(posedge clk or negedge rst_n)begin
  if(~rst_n)
  begin 
    rd_en_d1 <= 1'b0;
    rd_en_d2 <= 1'b0;
    rd_en_pos <= 1'b0;
  end
  else 
    begin 
    rd_en_d1 <= rd_en;
    rd_en_d2 <= rd_en_d1;
    rd_en_pos <= (rd_en_d1 |rd_en);
    end 
end
  

// assign rd_en_pos = rd_en_d1 & (~rd_en_d2);
always@(posedge clk or negedge rst_n)
begin
  if(~rst_n)
    frame_length_cnt <= 11'd0;
  else if(rd_en)
    frame_length_cnt <= frame_length_cnt + 11'd32;
  else 
    frame_length_cnt <= 11'd0;
end
//action_fifout_q
//删除[75]--复制[74]--重定向[73]--插、修、删[72:70]--字偏移[69:64]--掩码[63:32]--值[31:0]
always@(posedge clk or negedge rst_n)
begin
  if(~rst_n)
    begin
      word_offset <=  6'd0;
      value       <= 32'd0;
      mask        <= 32'd0;
      operation   <=  3'd0;
    end
  else if(bus_ctrl_cstate == IDLE && trans_start)
    begin
      word_offset <= action_fifout_q[69:64];
      value       <= action_fifout_q[31: 0];
      mask        <= action_fifout_q[63:32];
      operation   <= action_fifout_q[72:70];
    end
  else 
    begin
      word_offset <=  word_offset; 
      value       <=  value      ; 
      mask        <=  mask       ; 
      operation   <=  operation  ; 
    end
end
always@(posedge clk or negedge rst_n)
begin
  if(~rst_n) begin
      operation_d1   <=  3'd0;
      word_offset_d1 <=  6'd0;
      operation_d2   <=  3'd0;
    end
  else begin
      operation_d1   <= operation   ;
      operation_d2   <= operation_d1;
      word_offset_d1 <= word_offset ;
    end
end
//表示当前帧信息是否需要进行编码
//当前rd_data处的数据是frame_length_cnt为起点的数据
//word_offset以16bit为单位
always@(posedge clk or negedge rst_n)
begin
  if(~rst_n)
    action_en <= 1'b0;
  else if(action_fifout_q[72:70] != 3'b0 && action_fifout_q[69:68] == 2'b00 && bus_ctrl_nstate != IDLE && bus_ctrl_cstate == IDLE)
    action_en <= 1'b1;
  else if(operation != 3'b0 && rd_en  && (frame_length_cnt + 11'd64) > {2'h0,word_offset,1'b0}
         && frame_length_cnt+11'd32 <= {2'h0,word_offset,1'b0})
    action_en <= 1'b1;
  else 
    action_en <= 1'b0;
end

always@(posedge clk or negedge rst_n)
begin
  if(~rst_n) begin
    action_en_d1 <= 1'b0;
    action_en_d2 <= 1'b0;
  end
  else begin
    action_en_d1 <= action_en;
    action_en_d2 <= action_en_d1;
  end
end
//表示当前帧信息是否为编码帧信息之后的帧
always@(posedge clk or negedge rst_n)
begin
  if(~rst_n)
    action_last <= 1'b0;
  else if(bus_ctrl_cstate == IDLE && (~add_one_clk_d1))
    action_last <= 1'b0;
  else if(action_en_d1)
    action_last <= 1'b1;
  else 
    action_last <= action_last;
end

always@(posedge clk or negedge rst_n)
begin
  if(~rst_n)
    action_last_d1 <= 1'b0;
  else
    action_last_d1 <= action_last;
end

//正在工作，无法处理新的帧信息
always@(posedge clk or negedge rst_n)
begin
  if(~rst_n)
    trans_ready <= 1'b0;
  else if((bus_ctrl_nstate == IDLE && (~add_one_clk)) && rd_rdy )
    trans_ready <= 1'b1;
  else 
    trans_ready <= 1'b0;
end
always@(posedge clk or negedge rst_n)
begin
  if(~rst_n)
    frame_rd_end <= 1'b0;
  else if((bus_ctrl_nstate == IDLE) && (~add_one_clk))
    frame_rd_end <= 1'b1;
  else 
    frame_rd_end <= 1'b0;
end

//根据流分类的指令对数据帧进行增加/删除/修改操作
assign rd_data = (rd_en_d1==1'b1)?rd_data_i_sample : 263'h0;
always@(posedge clk or negedge rst_n)
begin
  if(~rst_n)
    data_reg <= 263'h0;
  else if(action_en_d1)
    case(operation_d1)
    3'b100://增加
      case(word_offset_d1[3:1])
        3'd0:
        data_reg <= {rd_data[262:256],value,rd_data[255:32]};
        3'd1:
        data_reg <= {rd_data[262:224],value,rd_data[223:32]};
        3'd2:
        data_reg <= {rd_data[262:192],value,rd_data[191:32]};
        3'd3:
        data_reg <= {rd_data[262:160],value,rd_data[159:32]};
        3'd4:
        data_reg <= {rd_data[262:128],value,rd_data[127:32]};
        3'd5:
        data_reg <= {rd_data[262: 96],value,rd_data[95:32]};
        3'd6:
        data_reg <= {rd_data[262: 64],value,rd_data[63:32]};
        3'd7:
        data_reg <= {rd_data[262: 32],value};
        default:
        data_reg <= rd_data;
      endcase
    3'b010://修改
      case(word_offset_d1[3:1]) 
        3'd0:
        data_reg <= {rd_data[262:256],(rd_data[255:224] & ~mask)^(value &mask),rd_data[223:0]};
        3'd1:
        data_reg <= {rd_data[262:224],(rd_data[223:192] & ~mask)^(value &mask),rd_data[191:0]};
        3'd2:
        data_reg <= {rd_data[262:192],(rd_data[191:160] & ~mask)^(value &mask),rd_data[159:0]};
        3'd3:
        data_reg <= {rd_data[262:160],(rd_data[159:128] & ~mask)^(value &mask),rd_data[127:0]};
        3'd4:
        data_reg <= {rd_data[262:128],(rd_data[127: 96] & ~mask)^(value &mask),rd_data[95:0]};
        3'd5:
        data_reg <= {rd_data[262: 96],(rd_data[ 95: 64] & ~mask)^(value &mask),rd_data[63:0]};
        3'd6:
        data_reg <= {rd_data[262: 64],(rd_data[ 63: 32] & ~mask)^(value &mask),rd_data[31:0]};
        3'd7:
        data_reg <= {rd_data[262: 32],(rd_data[ 31:  0] & ~mask)^(value &mask)};
        default:
        data_reg <= rd_data;
      endcase
    3'b001://删除
      case(word_offset_d1[3:1])
        3'd0:
        data_reg <= {32'h0,rd_data[262:256],rd_data[223:0]};
        3'd1:
        data_reg <= {32'h0,rd_data[262:224],rd_data[191:0]};
        3'd2:
        data_reg <= {32'h0,rd_data[262:192],rd_data[159:0]};
        3'd3:
        data_reg <= {32'h0,rd_data[262:160],rd_data[127:0]};
        3'd4:
        data_reg <= {32'h0,rd_data[262:128],rd_data[95:0]};
        3'd5:
        data_reg <= {32'h0,rd_data[262:96],rd_data[63:0]};
        3'd6:
        data_reg <= {32'h0,rd_data[262:64],rd_data[31:0]};
        3'd7:
        data_reg <= {32'h0,rd_data[262:32]};
        default:
        data_reg <= rd_data;
      endcase
    default:
      data_reg <= rd_data[262:0]; //带sop和eop信息
    endcase
  else 
    data_reg <= rd_data[262:0];
end
//需要增加字段的情况下，需要将当前帧信息的最后四字节存储
always@(posedge clk or negedge rst_n)
  if(!rst_n)
    data_reg_d1 <= 32'd0;
  else if(rd_en_d1 && operation_d1[2]==1'b1)
    data_reg_d1 <= rd_data[31:0];
  else 
    data_reg_d1 <= data_reg_d1;

always@(posedge clk or negedge rst_n)
  if(!rst_n)
    data_reg_d2 <= 32'd0;
  else 
    data_reg_d2 <= data_reg_d1;

//删除情况下，将255-31的数据打拍存储
//假如第一组数据删除了32bit，那么第二组数据向前补32bit数据，剩下的帧信息就要存储起来和第三组帧信息一起发送
always@(posedge clk or negedge rst_n)
  if(!rst_n)
    rd_data_d1 <= 224'd0;
  else if((action_en_d1 || action_last) && operation_d1[0]==1'b1)
    rd_data_d1 <= rd_data[223:0];
  else 
    rd_data_d1 <= 224'h0;
//总线搬移的数据信号
//rd_data[262:256]为控制位，修改删除增加均不能改变控制位信息！！
//删除情况下，如果前256bit删除了某字段，后边的帧信息向前补齐，但是不能补控制信息，只能补数据信息
//同时控制信息中的mod信息也需要变化
//增加字段的情况相同
//同时控制信息中的mod信息也需要变化
//控制信号更改麻烦，可以采取增加新的控制信号的方式！！！
//仅获取数据信息
always@(posedge clk or negedge rst_n)
  if(~rst_n)
    bus_data_r <= 256'd0;
  else if(action_en_d2 && bus_flag_d2)
    case(operation_d2)
    3'b100:bus_data_r <= data_reg[255:0]; 
    3'b010:bus_data_r <= data_reg[255:0];
    3'b001:bus_data_r <= {data_reg[223:0],rd_data[255:224]}; //删除情况下，
    default:bus_data_r<= 256'd0;
    endcase
  else if(action_last_d1 && bus_flag_d2)
    case(operation_d2)
    3'b100:bus_data_r <= {data_reg_d2,data_reg[255:32]};
    3'b010:bus_data_r <= data_reg[255:0];
    3'b001:bus_data_r <= {rd_data_d1,rd_data[255:224]};
    default:bus_data_r <= 256'd0;
    endcase
  else
    bus_data_r <= data_reg[255:0];
//增加控制信息
//帧起始信息
always@(posedge clk or negedge rst_n)
  if(~rst_n)
    sop <= 1'b0;
  else if(rd_en_pos)
    sop <= 1'b1;
  else 
    sop <= 1'b0;
//帧终止信息
always@(posedge clk or negedge rst_n)
  if(~rst_n)
    eop <= 1'b0;
  else if(data_end)
    eop <= 1'b1;
  else 
    eop <= 1'b0;
//帧mod信息
always@(posedge clk or negedge rst_n)
  if(~rst_n)
    mod <= 5'b0;
  else if(data_end)
    mod <= frame_length_r_d2[4:0];
  else 
    mod <= 5'b0;
assign bus_data_o =(bus_data_val_o==1'b1)?{sop,eop,mod,bus_data_r}:262'h0;
//搬移的总线计数
always@(posedge clk or negedge rst_n)
  if(~rst_n)
    frame_cnt_send <= 11'd0;
  else if(rd_en_d1) 
    frame_cnt_send <= frame_cnt_send + 11'd32;
  else 
    frame_cnt_send <= 11'd0;
always@(posedge clk or negedge rst_n)
  if(~rst_n)
    data_end <= 1'b0;
  else if(frame_cnt_send + 11'd32 >= frame_length_r_d1 && frame_cnt_send < frame_length_r_d1)
    data_end <= 1'b1;
  else 
    data_end <= 1'b0;
//总线数据有效信号
always@(posedge clk or negedge rst_n)
  if(~rst_n)
    bus_data_val_o <= 1'b0;
  else if(bus_flag_d2)
    if(eop)
      bus_data_val_o <= 1'b0;
    else
      bus_data_val_o <= rd_en_d2 | data_end;
  else 
    bus_data_val_o <= 1'b0;
//总线数据结束信号
always@(posedge clk or negedge rst_n)
  if(~rst_n)
    bus_data_end_o <= 1'b0;
  else
    bus_data_end_o <= data_end;

//总线的长度信息
assign frame_len_bus = (bus_flag_d1)?frame_length_r_d1:11'd0;
//捕获至CPU的数据信号和总线搬移的信号一样，支持修改、删除和增加操作
always@(posedge clk or negedge rst_n)
  if(~rst_n)
    capture_data_r <= 256'd0;
  else if(action_en_d2 && cap_flag_d2)
    case(operation_d2)
    3'b100:capture_data_r <= data_reg[255:0];
    3'b010:capture_data_r <= data_reg[255:0]; 
    3'b001:capture_data_r <= {data_reg[223:0],rd_data[255:224]}; //删除情况下，
    default:capture_data_r<= 256'd0;
    endcase
  else if(action_last_d1 && cap_flag_d2)
    case(operation_d2)
    3'b100:capture_data_r <= {data_reg_d2,data_reg[255:32]};
    3'b010:capture_data_r <= data_reg[255:0];
    3'b001:capture_data_r <= {rd_data_d1,rd_data[255:224]};
    default:capture_data_r <= 256'd0;
    endcase
  else
    capture_data_r <= data_reg[255:0];
assign capture_data_o =(capture_dval==1'b1)?{sop,eop,mod,capture_data_r}:263'h0;
//捕获数据有效信号
always@(posedge clk or negedge rst_n)
  if(~rst_n)
    capture_dval <= 1'b0;
  else if(cap_flag_d2)
    if(eop)
      capture_dval <= 1'b0;
    else  
      capture_dval <= rd_en_d2 | data_end;
  else 
    capture_dval <= 1'b0;
assign cpt_en = (cap_flag_d1|cap_flag_d2)?1'b1:1'b0;
assign cpt_frame_len = (cap_flag_d1|cap_flag_d2)?frame_length_r_d1 :11'd0;
//fifo中大于等于3个数据时输出满信号,写入的为帧长信息
//改为首字置出fifo
/*frame_len_fifo U_frame_len_fifo2(
                 .clock(clk),
                 .rst_n(rst_n),
                 .fifo_wen(frame_length_valid),
                 .fifo_wdata(frame_length),
                 .fifo_ren(frame_length_ren),
                 .fifo_rdata(frame_length_rd),
                 .fifo_empty_rd(),
                 .almost_full()          
                 );*/
  fifo_wxx_dxx_s #(
      .PTR(6),
      .WORDS(64),
      .W_SIZE(11),
      .A_FULL(63)
    ) inst_frame_len_fifo2 (
      .clock         (clk),
      .rst_n         (rst_n),
      .fifo_wen      (frame_length_valid),
      .fifo_wdata    (frame_length),
      .fifo_ren      (frame_length_ren),
      .fifo_rdata    (frame_length_rd),
      .fifo_empty_rd (/*fifo_empty*/),
      .almost_full   (/*fifo_full*/)
    );

`ifndef ASIC
//-----------------------mark debug-------------------------
(*mark_debug = "true"*) reg [31:0] fp_bus_discard_cnt;

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        fp_bus_discard_cnt <= 32'd0;
    end
    else if (rd_data_i_sample[261] && bus_ctrl_cstate == DISCARD) begin
        fp_bus_discard_cnt <= fp_bus_discard_cnt + 32'b1;
    end
    else begin
        fp_bus_discard_cnt <= fp_bus_discard_cnt;
    end
end

(*mark_debug = "true"*) reg [31:0] fp_bus_cap_cnt;

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        fp_bus_cap_cnt <= 32'd0;
    end
    else if (rd_data_i_sample[261] && bus_ctrl_cstate == CAPTURE_TRANS_UP) begin
        fp_bus_cap_cnt <= fp_bus_cap_cnt + 32'b1;
    end
    else begin
        fp_bus_cap_cnt <= fp_bus_cap_cnt;
    end
end

(*mark_debug = "true"*) reg [31:0] fp_bus_cap_trans_cnt;

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        fp_bus_cap_trans_cnt <= 32'd0;
    end
    else if (rd_data_i_sample[261] && bus_ctrl_cstate == BUS_CAPTURE_TRANS) begin
        fp_bus_cap_trans_cnt <= fp_bus_cap_trans_cnt + 32'b1;
    end
    else begin
        fp_bus_cap_trans_cnt <= fp_bus_cap_trans_cnt;
    end
end


(*mark_debug = "true"*) reg [31:0] fp_bus_trans_cnt;

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        fp_bus_trans_cnt <= 32'd0;
    end
    else if (rd_data_i_sample[261] && bus_ctrl_cstate == BUS_TRANS) begin
        fp_bus_trans_cnt <= fp_bus_trans_cnt + 32'b1;
    end
    else begin
        fp_bus_trans_cnt <= fp_bus_trans_cnt;
    end
end
`endif

endmodule
